For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various impediments to continued scaling have been predicted for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, the development of further methods for improving performance, in addition to scaling, has become critical. One such method involves using high mobility materials, other than silicon, for CMOS such as Group III-V semiconductors or SiGe or Ge.
Methods for fabricating Fin structures on an insulator structure (where the Fin can be composed of, for example, SiGe, Ge, and Group III-V semiconductor materials) are currently being explored. In those cases where wafer bonding techniques are used followed by Fin patterning a problem can arise that is related to a presence of crystalline defects in the Fin material. Another problem area relates to Fin patterning issues such as Fin taper, Fin sidewall roughness, reactive ion etching (RIE) damage and post RIE cleaning.